Draft Summary: WP#32 14.06.2007 on LCTPC electronics/advanced endcap Dear LCTPC friends, Here is a draft summary of the electronics meeting on 14.06.2007. Comments are welcome. Best greetings, Luciano and Ron WP#32: LCTPC electronics meeting #1 14/06/2007 -------------------------------------------- Thursday 14 June 2007 West Coast East Coast W.Europe Japan 07.00 10.00 16.00 23.00 Agenda -------------------- 1. CERN: developments - Luciano,Gerd,Franca 2. Lund: programming of the preamplifier - Leif 2a. Lund: proposal to introduce an additional FEC - Ulf 2b. Lund: proposal to introduce an additional FEC - Ulf 3. Saclay: ideas - Paul 4. Carleton/Montreal: R&D work - Jean-Pierre or Madhu 5. Rostock: R&D work - Sasha 6. AOB Reminder of the suggested steps this year (subject to change): --June 14: Video/phone meeting with prepared talks (today). --July 26: Video/phone meeting with prepared talks. --After the October 8-10 Eudet annual meeting in Paris. Face-to-face "Advanced-endcap" meeting on October 10 afternoon and October 11 morning with prepared talks. Attendees (sorry, the names of individuals from the different labs were not noted down): -Carlton -Saga -Lund -Nikhef -Desy -MPI -Saclay -CERN -Kek (phone) Summary ---------------- The talks are to be found at http://ilcagenda.linearcollider.org/conferenceDisplay.py?confId=1660 1a. Luciano (slides 1-7) explained the goals and listed the properties of the general purpose charge readout chip for the design team at CERN (Gerd Trampisch, Hugo Franca Santos, Attiq Ur Rehman: --130nm technology --highly integrated analog/digital parts --programmability --1 channel/mm^2 --32 or 64 channels per chip --signal: 10^2 to 10^7 electrons --capacitance: 0.1 to 10. pF --peaking time 20-100ns --digitize 40-160MHz The near-term goal is to be ready for a submission in the 4th quarter this year. 1b. Gerd covered details of the programmable preamp. It consists charge-sensitive amplifier, pole-zero cancellation and low-pass filtering stages before the ADC. The prototype built in 2006 works as planned for 0-200fC and has noise of 250e at 10pF. A new PASA summarized on slide 14 (details on slides 15-25) was submitted in May 2007 and will be used for the LP1. The point that it can be programmed to have a risetime as fast as 10ns was followed a long discussion about the speed needed for the signal. Luciano said the peaking time 20-100ns was recommended at the Amsterdam Eudet meeting in January 2006, while at our WP phonemeetings last fall Madhu pointed out that in practice signals faster than 200ns occur rarely, due to diffusion or to track dip-angle. So is the circuit overdesigned? Since the circuit design is finished, the fact that it can be fast is also good for 2-track resolution and gives flexibility. (Note added by RS: 200ns may be what is expected for a track from the IP, but the LCTPC should also try "to expect the unexpected". For example some Susy models allow really-long-lived particles; one might imagine a topology a very heavy long-lived particles decays into a hadron that travels parallel to an endplate at very short drift distance, i.e. small drift and small dip-angle.) Jean-Pierre questioned the wisdom of using NMOS (slide 25). Gerd and Luciano answered that the noise is only slightly higher, but Leif's life is then easier since there is one less voltage to provide. 1c. Hugo reviewed the technique for the ADC (slides 26-30). 2. Leif first asked details about programming the preamp which Luciano answered. 2a/b. Ulf described the DAQ being developed for the LP, which is based on the ALICE TPC DAQ in the LP1 at Desy meeting on 4 June. Today he summarized proposals for a) the distribution of trigger signals and b) a modified FEC. 3. Paul again covered a) the layout of the LP1 panel with bulk-micromegas+resistive-anode and b) the use of T2K electronics for LP1. a) Now that the panel size has converged, detailed design work (slides 3,9,10,11) will be started. b) An alternative to the new_preamp-ALTRO line is to use the T2K-AFTER approach (slides4-8) which is thought to be cheaper, athough ALTRO is officially specified by EUDET. The proposal is that this should be kept as a back-up, and that (slide 10) panels with ALTRO be prepared at Carleton and ones with AFTER at Saclay. 4. Madhu described the electronics development at Carleton/Montreal. Details are give in slides2,3,4 and summarzed in slide5: 48 channel VME card with 10 bit FADC derived from new generation development of 12-bit 50MS/s digitizers. A 16-channel prototype is being fabricated which could be made plug-compatible with the ALTRO. Power pulsing will be included in the next generation of 128 channels which could be tried out on a SP, which the ensuing discussion concluded is a good idea. 5. Sasha reviewed the Rostock work on time-to-charge conversion TDC approach for LCTPC for which a few hundred channels are part of the EUDET programm. Madhu ask about the resolution as function of drift distance, which Sasha agreed needs to be studied with data and simulation.