Summary of discussion at CALICE DAQ Task Force meeting, 27/Jun/2016

Attendees: R. Cornat, M. Reinecke, J. Kvasnicka, A. Irles, K. Krueger, L. Mirabito, C. Combaret, D. Cussans, T. Coates, M. Wing, T. Suehara

1. Master CCC
 - Clock: 50 MHz (for Silicon and SDHCAL) and 40 MHz (AHCAL)
 - Consider combined firmware which can work as both TLU and Master CCC
 - Platform will be the new TLU board (with Artix)
 - Hardware available at around end of August
 - Will not be used for the Si+SDHCAL TB on October
2. EUDAQ 2.x
 - Will be released after test at AHCAL test beam in end of July
 - Integration of SDHCAL will be tested soon after the release
   with help of EUDAQ people
3. Interface document
 - Discussion of responsibility of adaptation
   Main part should be implemented in Master CCC (or TLU if combined)
 - Running mode will be modified to accept CALICE TB mode with busy handling
 - Second draft will be circulated
4. Next meeting
 - In August, after AHCAL test beam, doodle will be circulated


Resource list

- Silicon

Core DAQ:
DQM4HEP repositories

- EUDAQ for LC

There are minutes attached to this event. Show them.
    • 11:00 11:10
      SiECAL news 10m
      Speakers: Dr Frédéric Magniette (LLR, CNRS) , Dr Remi Jean Noel Cornat (CNRS/IN2P3/Laboratoire Leprince-Ringuet (LLR)) , Dr Taikan Suehara (Kyushu University)
    • 11:10 11:20
      AHCAL/ScECAL news 10m
      Speakers: Jiri Kvasnicka (Acad. of Sciences of the Czech Rep. (CZ)) , Mr Jiri Kvasnicka (Institute of Physics, ASCR) , Mr Mathias Reinecke (DESY)
    • 11:20 11:30
      SDHCAL news 10m
      Speakers: Mr Christophe Combaret (IPNL) , Laurent Mirabito (Institut de Physique Nucleaire de Lyon (IPNL)-Universite Claude)
    • 11:30 12:30
      Discussion 1h
      Speaker: Dr Taikan Suehara (Kyushu University)