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Summary of discussion at CALICE DAQ Task Force meeting, 27/Jun/2016
Attendees: R. Cornat, M. Reinecke, J. Kvasnicka, A. Irles, K. Krueger, L. Mirabito, C. Combaret, D. Cussans, T. Coates, M. Wing, T. Suehara
1. Master CCC
- Clock: 50 MHz (for Silicon and SDHCAL) and 40 MHz (AHCAL)
- Consider combined firmware which can work as both TLU and Master CCC
- Platform will be the new TLU board (with Artix)
- Hardware available at around end of August
- Will not be used for the Si+SDHCAL TB on October
2. EUDAQ 2.x
- Will be released after test at AHCAL test beam in end of July
- Integration of SDHCAL will be tested soon after the release
with help of EUDAQ people
3. Interface document
- Discussion of responsibility of adaptation
Main part should be implemented in Master CCC (or TLU if combined)
- Running mode will be modified to accept CALICE TB mode with busy handling
- Second draft will be circulated
4. Next meeting
- In August, after AHCAL test beam, doodle will be circulated
Resource list
- Silicon
http://llr.in2p3.fr/sites/pyrame/calicoes/index.html
- SDHCAL
Core DAQ:
https://github.com/mirabitl/levbdim
SDHCAL DAQ:
https://github.com/mirabitl/SDHCAL
DQM4HEP repositories
https://github.com/DQM4HEP
- EUDAQ for LC
https://github.com/EUDAQforLC