Attendees: R. Cornat, F. Magniette, J. Kvasnicka, R. Mathias, L. Mirabito, C. Combaret, T. Suehara, V. Balagura
1. News from each technology - see slides for detail
- Si: Calicoes with spiroc2 tested successfully.
- Sc: Start_readout omitted. Wing-LDA ongoing.
- SDHCAL: Hardware in CERN until next TB.
2. Discussion about clock (page 4 of discussion slide)
- Agreed on having a master clock
- Master clock will be provided from master CCC to individual CCCs
- 5 MHz (assumed to be BX clock) is best for the common clock
- Condition of each technology accepting the master clock
-- Si: Should be LEMO (or SMA) input. HDMI input available but not tested.
Need conversion to 50 MHz since CCC has no PLL.
-- Sc: No clock input now. Need to design a new mezzanine for Zedboard.
Either HDMI or LEMO can be accepted. 5 MHz OK.
-- SDHCAL: HDMI input desired (LEMO possible but only 2 ports available).
5MHz is OK (Currently 50 MHz, but can be changed).
3. AOB
- Will continue discussions in next meeting. Comments of slides welcome.
- Next meeting will be early April. Doodle will come as usual.