Speaker
Caterina Vernieri
(SLAC National Accelerator Laboratory (US))
Description
We report on the NAPA (Nanosecond timing Pixel for large Area sensors) detector program—comprising prototype chips NAPA‑p1 and NAPA‑p2—designed for future e⁺e⁻ colliders. We will report on the test results of NAPA‑p1, fabricated in 65 nm CMOS with a 1.5 mm × 1.5 mm footprint and 25 µm pitch as well as the new design of NAPA‑p2. To achieve an improvement in timing resolution and power efficiency over the current state-of-the-art, we are developing a compact, low-power Time-to-Digital Converter (TDC) and are working to integrate the full TDC into a MAPS pixel design, addressing the tight area, routing, and power constraints.
Author
Caterina Vernieri
(SLAC National Accelerator Laboratory (US))
