8–11 Jul 2024
The University of Tokyo, Japan
Asia/Tokyo timezone

Next Generation LLRF Control Platform for Compact C band Linear Accelerator

10 Jul 2024, 12:00
20m
1320 (Science building n.4 (CHANGED))

1320

Science building n.4 (CHANGED)

Oral presentation (in person) Normal Conducting RF Normal conducting RF

Speaker

Chao Liu (SLAC National Accelerator Laboratory)

Description

The Low-Level RF (LLRF) control circuits of linear accelerators (LINACs) are conventionally realized with heterodyne based architectures, which have analog RF mixers for up and down conversion with discrete data converters. We have developed a new LLRF platform for C band linear accelerator based on the Frequency System-on-Chip (RFSoC) device from AMD Xilinx. The integrated data converters in RFSoC can directly sample the RF signals in C band and perform the up and down mixing digitally. The programmable logic and processors required for signal processing for LLRF control system are also included in a single RFSoC chip. With all the essential components integrated in a device, the RFSoC-based LLRF control platform can be implemented more cost-effectively and compactly, which can be applied to a broad range of accelerator applications. In this paper, the structure and configuration of the newly developed LLRF platform will be described. We have performed a detailed performance evaluation based on the requirements of C band linear accelerators and part of the characterization results will be presented and discussed.

Primary author

Chao Liu (SLAC National Accelerator Laboratory)

Co-authors

Emilio Nanni (SLAC National Accelerator Laboratory) Larry Ruckman (SLAC National Accelerator Laboratory) Ryan Herbst (User)

Presentation materials

Peer reviewing

Paper